IP Lock is FPGA logic security system which used very reliable AES encryption
technology. IP properties in FPGA are protected from illegal copy by only
including IP Lock in FPGA and connecting with encryption controller chip.
Demo video on youtube
AES(Advanced Encryption Standard) is common key cryptosystem chosen by NIST, US. Both encryption and decryption are high speed. And it is also stronger than triple DES. So it is noticed as encryption standard for next generation replaced with DES. Currently AES is adopted with security for financial system, LAN system and so on.
Laboratories pack contains encryption chips which are already written unique ID at shipment
by Design Gateway. No one can rewrite this fixed ID key. To avoid duplication,
each Laboratories pack have different unique ID key, so user must use IP
Lock core with encryption chips in same package. Design Gateway provide
encryption chip 10pcs package (IPL-010L) and 30pcs package (IPL-030L).
This product is suitable for prototype and small lot usage.
Contents of Laboratories pack:
Writer pack is suitable for mass production. User can write any ID key to blank encryption chip by using IP Lock write. User can set and write optional ID key for each products or lot.
Writer pack contains blank chip 3pcs. For mass production, Design Gateway provide blank chip (IPL-CHP, MOQ=100pcs).
Contents of Writer pack (IPL-003WR):